The present invention concerns an accurate timing model for logic simulation of integrated circuits which takes into account process, temperature and power supply variations.
When designing an integrated circuit, it is generally desirable to simulate the functioning of logic circuitry within the integrated circuit. In order to accurately access the performance of the circuitry, it is additionally desirable that the logic simulation of logic include an accurate assessment of timing delays through the circuitry, at least in the critical paths.
In general, timing delays through circuitry are caused by propagation delays through and between logic cells which comprise the circuitry. The actual amount of propagation delay through and between logic cells is generally dependent on various capacitances within and between the logic cells, as well as the current available to charge or discharge the capacitances.
When developing a timing model, it is desirable to take into account the time delay introduced by charging the input capacitance of logic cells. This time delay is directly affected by the input current available to charge the input capacitance to the logic cell. This input current, in turn, is directly affected by the fan out of the output of the logic cell providing the input current.
In addition, process, temperature and power supply variations can also affect timing models. In the prior art, overall scaling factors have been used to take these into account. However, because different logic cells react differently to process, temperature and power supply variations, this has proved inaccurate. Alternately, it is possible to characterize every cell in a cell library at multiple process, temperature and power supply conditions. See R. W. Phelps, Advanced Library Characterization for High Performance ASIC, Proceedings of the IEEE International Asic Conference, 1991, pp. P15-3.1 through P15-3.4. While this does provide for a more accurate means to determine the effect of process, temperature and power supply variations, there is an enormous increase in the characterization time to determine the parameters.